This invention relates to a semiconductor device and a method of manufacturing the same. More specifically, this invention relates to transistors arranged with high-density by the use of silicon selective growth technique and contact formation technique based on self-alignment, and a method of manufacturing the same.
In order to achieve high-density in the semiconductor device, the recent trend is directed to the miniaturization technique of the devices. For achieving the device with a greater scale of high-density, a mask alignment margin between a contact and an underlayer wiring pattern has been reduced.
As a method of reducing such mask alignment margin, a technique for forming the contact by the use of the self-alignment is exemplified.
In the technique, the underlayer wiring pattern is covered with a silicon nitride film and the contact is opened by etching having a high-etching selective ratio between the silicon oxide film as an interlayer insulating film and the silicon nitride film for protecting the underlayer wiring pattern. Such conventional technique is disclosed in, for example, Japanese Unexamined Patent Publication (JP-A) No. Hei. 9-213949.
Referring now to FIGS. 1A through 1E, the conventional technique will be described below.
At first, a gate oxide film 2 is deposited on a semiconductor substrate 1 as illustrated in FIG. 1A. Thereafter, a polysilicon film 3 and a silicon nitride film 24 are sequentially deposited thereon, and an unnecessary portion is removed by the use of photolithography and anisotropic dry etching. Thereby a gate electrode made of the polysilicon film 3 is formed such that the silicon nitride film 24 is laminated or stacked thereon. Next, a low-concentration impurity region 10 is formed on the semiconductor substrate 1 by using ion implantation.
Successively, a silicon nitride film 5 is deposited on a whole surface, as illustrated in FIG. 1B.
Then the silicon nitride film 5 is partially etch-backed by the use of the anisotropic dry-etching such that a sidewall film 6 is left only on a sidewall portion of the gate electrode, as illustrated in FIG. 1C. Thereafter, a high-concentration impurity region 11 is formed by the ion implantation.
Successively, an interlayer insulating film 7 as the silicon oxide film is entirely deposited thereon, and a contact hole 8 is opened by removing an unnecessary portion by the use of the photolithography and the anisotropic dry-etching, as illustrated in FIG. 1D.
In such anisotropic dry-etching, an etching rate of the silicon nitride film is lower than that of the silicon oxide film so that an etching selective ratio becomes higher.
As a consequence, even when an upper opening dimension of the contact hole 8 is larger than a space between the sidewall films 6 of adjacent gate electrodes, the gate electrode is protected by the silicon nitride film 24 and the sidewall film 6 so that the gate electrode is not electrically shorted with a wiring layer 9 which will be formed later.
Next, a conductive film is deposited on the whole surface, and the wiring layer 9 is formed by removing an unnecessary portion by the photolithography as well as the anisotropic dry-etching, as illustrated in FIG. 1E.
In the above-described conventional technique, however, the silicon nitride film, which readily traps a hot electron, is used as the sidewall film 6 of the gate electrode. Consequently, a transistor characteristic is easily deteriorated. The above-mentioned conventional publication also discloses a method of solving such a problem, and this method will be explained with reference to FIGS. 2A through 2G.
At first, the gate oxide film 2 is deposited on the semiconductor substrate 1, as illustrated in FIG. 2A. Thereafter, the polysilicon film 3 and the silicon nitride film 4 are sequentially deposited thereon, and an unnecessary portion is removed by the photolithography and the anisotropic dry-etching. Thus, the gate electrode as the polysilicon film 3, on which the silicon nitride film 4 is laminated, is formed.
Next, the low-concentration impurity region 10 is formed in the semiconductor substrate 1 by the ion implantation.
Subsequently, the silicon oxide film 12 is deposited on the whole surface, as illustrated in FIG. 2B.
Successively, the silicon oxide film 12 is partially etch-backed by the use of the anisotropic dry-etching so that a first sidewall film 13 is left only on the sidewall portion of the polysilicon film 3 as the gate electrode, as illustrated in FIG. 2C.
In such anisotropic dry-etching, the etching selective ratio between the silicon oxide film and the silicon nitride film becomes high. As a result, while the first sidewall film 13 has the substantially same height as that of the polysilicon film 3 by adjusting etching time, a film thickness of the silicon nitride film 4 on the polysilicon film 3 is not largely reduced. Thereafter, the high-concentration impurity region 11 is formed by using the ion implantation.
Subsequently, the silicon nitride film 15 is deposited on the whole surface with the substantially same film thickness as that of the sidewall film 13, as illustrated in FIG. 2D.
Next, the silicon nitride film 15 is partially etch-backed by using the anisotropic dry-etching so that a second sidewall film 16 is left only on the sidewall portion of the silicon nitride film 4 on the gate electrode and the polysilicon film 3 as the gate electrode, as illustrated in FIG. 2E. In this event, the etching time is adjusted such that the silicon nitride film 15 is not left on the side surface of the first sidewall film 13.
Successively, the interlayer insulating film 7 as the silicon oxide film is deposited on the whole surface, and the contact hole 8 is opened by removing an unnecessary portion by the use of the photolithography and the dry-etching, as illustrated in FIG. 2F.
In such anisotropic dry-etching, the etching selective ratio between the silicon oxide film and the silicon nitride film is selected to a high value. Thereby, even if the upper opening of the contact hole 8 has the dimension larger than the space between the sidewall films 6 of the adjacent gate electrodes, the gate electrode is protected by the silicon nitride film 4, the first sidewall film 13 and the second sidewall film 16. As a consequence, the gate electrode is not electrically shorted with the wiring film which will be formed later.
Next, the conductive film is deposited on the whole surface, and the wiring layer 9 is formed by removing an unnecessary portion by using the photolithography and the anisotropic dry-etching, as illustrated in FIG. 2G.
By employing the above-described technique, both the first sidewall film 13 and the second sidewall film 16 are placed between the polysilicon film 3 as the gate electrode and the wiring layer 9. In consequence, even when the dimension of the upper opening of the contact hole 8 is larger than the space between the sidewall films of the adjacent gate electrodes, the gate electrode is not electrically shorted with the wiring layer 9.
Further, the lower portion of the sidewall film of the gate electrode is formed of the silicon oxide film. Thereby, the hot carrier can not be readily trapped as compared with the case of the silicon nitride film. Therefore, the transistor characteristic is not easily deteriorated.
Upon formation of the second sidewall film 16, the etch-back must be carried out so that the silicon nitride film 15 formed on the side surface of the first sidewall film 13 is completely removed.
However, the silicon nitride film 15 may be partially left on the side surface of the first sidewall film 13 in the practical use in the cause of variation of the film thickness of the silicon nitride film 15 and variation of the anisotropic dry-etching rate upon etch-back.
Under such circumstances, the bottom portion of the contact hole 8 becomes smaller in dimension than the predetermined value, so that contact resistance is increased inevitably.
Upon the etch-back of the silicon nitride film 15, the surface of the high-concentration impurity region 11 is subjected to etch-back atmosphere during long time, resulting in etching damage. As a consequence, the transistor characteristic is degraded.
In addition, the first sidewall film 13 is formed of the silicon oxide film. Therefore, the first sidewall film 13 is also etched in a step of processing hydrofluoric acid chemical liquid for removing a natural oxide film on the bottom portion of the contact before forming the wiring layer. Consequently, the polysilicon film 3 may be electrically shorted with the wiring layer 6
Depending upon the kinds of products, only the low concentration impurity regions 10 are used as source/drain regions of the transistor but the high concentration impurity regions may be not formed.
For example, a dynamic random access memory (DRAM) adopts such a structure in order to reduce a leak current in a reverse direction at a PN junction between an N-type low concentration impurity regions 10 as source/drain regions and a P-well region in many cases.
With this structure, it is difficult to employ metal material for the wiring layer 9. This reason will be explained below. Namely, in case where a silicide layer as compound of metal and silicon is formed between the wiring layer 9 and the low concentration impurity region 10, a depletion layer formed at the PN junction is widely extended towards an N-side so that the silicide layer is entrapped inside the depletion layer.
The silicide layer can serves as a generation recombination center, that is, a GR center, and therefore, the leak current in the reverse direction is increased. The wiring layer 9 is often made of the polysilicon such that no silicide layer is formed between the wiring layer 9 and the low concentration impurity region 10. In this case, the contact resistance is increased in comparison with the metal wiring layer.